资源列表
9_TheBell
- FPGA，VHDL语言 蜂鸣器 响0.5S~~，时钟分频源程序，适用于所有FPGA芯片-FPGA, VHDL language buzzer 0.5S ~ ~, clock divider source, applicable to all FPGA chip! !
1_Lit_OneLED
- FPGA，VHDL语言，静态点亮一个LED，VHDL源程序~~~Quartus II软件-FPGA, VHDL language, static light a LED VHDL source code ~ ~ ~ applies to all FPGA chip! ! !
Proj
- 读AD数据后，写CF卡控制，可调整采集速率和存储速率-AD data is read, write CF card control, adjustable acquisition rate and storage rate
2025L
- 2025驱动程序很好用的很难找的我们找了好久才找到的希望对大家有帮助-The 2025 driver good with hard to find we are looking for a long time to find the hope to help
LFSR_FIFO_GasP
- • LFSR uses global clock > Every stage contains valid data > Data moves in lock-step > Bit sequencing and synchronization implicitly enforced • Async implementation requires explicit control > Not every stage contains
DVB
- This for the symbol interleaver. Wire permutation and the symbol intrleaver are present here.-This is for the symbol interleaver. Wire permutation and the symbol intrleaver are present here.
shift_arr
- This contains the shift array which can be used in 2D DCT with help of 2 1D DCTs.
PLB_MG
- PLB Macrogate in VHDL
Killswitch
- 这是用来KILLSWITCH的开关， 是采用汇编语言的编写。-This is used to to KILLSWITCH the switch, and is written in assembly language.
FIFO
- FIFO在VHDL上的实现。没有注释，较为完善，已通过编译。-FIFO implementations in VHDL. No comment, more perfect, has compiled.
FPGA_RS232
- FPGA芯片,利用Verilog硬件描述语言实现与PC电脑通信功能。-FPGA chip, the Verilog hardware descr iption language and PC computer communication function.
test_ddr2_mem_model
- ddr2 test bench top for altera fpga.-ddr2 test bench top for fpga.