资源列表
DM9000A
- DM900 100M物理层PHY芯片FPGA连接，fpga实现数据链路层功能，完成网络数据的收发-DM900 100M physical layer PHY chip FPGA connections, fpga data link layer, the completion of the network to send and receive data
sdr_verilog_lattice
- Verilog控制SDRAM-Verilog control SDRAM
mux8to1_with_if
- this code to input 8 different data and make them out sequentialy -this code to input 8 different data and make them out sequentialy
clock-verilog
- 数字钟，功能：12时/24时切换显示，校时,时间很准（4位数码管显示），内含sof，pof，tcl，四个文件，在开发板C1上已实现-digital clock ，
I2C
- 本源代码中用Verilog HDL语言编写了I2C的顶层及子模块文件，详细完整，并在Altera实验板上得以验证-primitive code discribe the I2C s function using the Verilog HDL language, the code are particular and integrity,moreover it has been validated in the altera FPGA and passed
modelsim8255
- this a programmed VHDL source for intel 8255,I have made some process in some details,I hope your all will like it!-this is a programmed VHDL source for intel 8255,I have made some process in some details,I hope your all will like it!
2345676588FPGAxiebofenxi
- 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using
AHB_APB_leon_1.tar
- for ahb with apb using leon
e1_framer
- E1 DeFramer :A design for Framing Telecom E1 Interface
Lock-source
- （1）通过8279的功能连接4*4的键盘和8位LED数码显示管，实现密码的键盘输入，数码管输出，并具备简单的功能键。 （2）利用步进电机模拟开门过程，在密码输入正确时启动，在接收到外部中断时停止。 （3）具有按键发声功能。 （4）密码错误时具有警报和警灯的，并且实现三次错误锁定的功能。 （5）通过INTR0实现系统的整体硬性复位。 （6）通过RT12864HZ控制LCD实现相关信息的提示。 （7）通过修改汇编程序中密码输入子程序本身达到修改密码的目的。 -(1) th
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
mul_algo
- contains codes for various multiplication algorithms and their reports for analysis