资源列表
dccount
- 直流电机控制，与步进电机控制有很大的区别-DC motor control, and stepper motor control are vastly different
ISP1362.rar
- 开发环境：QUARTUS ，sopc中isp1362鼠标控制器件的模块的源码，可以作为模块进行加载。,sopc code for isp1362，USB contoller can be a moudle
lampa_rgb_na_pilota_v1.1
- Lampka rgb na pliota, moż liwoś ć sterowania na odległ oś ć lamoka która ś wieci w kilku kolorach zielony niebieski czerwony-Lampka rgb na pliota, moż liwoś ć sterowania na odległ oś ć lamoka któr
ddr_kongzhiqi
- fpga上用verilog HDL实现的ddr控制器，简单易懂，适合新手参考-FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
lfsr-counter
- descr iption for LFSR counter
simu
- the document describe the langage vhdl
netlist8
- vhdl program of matlab file converted to vhdl
AnumberrT
- AT89S52控制64*16双基色点阵led显示数字数字通过过自摸取出数组8*16硬件环境：595，AT89S52,138 -AT89S52 control 64* 16 dual color dot matrix led display digit number by Zimo remove an array of 8* 16 Hardware Environment: 595, AT89S52 is, 138
DP
- TIC6000系列 C67浮点DSP处理器 派发站源代码-TIC6000 floating-point DSP processor series C67 station source code distributed
DCHUFAQI
- 一个典型的时序元件D触发器的VHDL描述,希望对大家有帮助-A typical time-series components of the VHDL descr iption of D flip-flop
sdram
- 在ISE环境中，利用verilog语言编写的SDRAM的控制，已经通过功能仿真，其中PLL部分并没有加入，使用时可以自行加入PLL模块。-Verilog language in the ISE environment, the use of SDRAM control, through functional simulation, which the PLL part and did not join, can join the PLL blocks.
fulladd
- 用于实现两个数相加的vhdl代码，在相应的编译器中使用-used to achieve the two summed VHDL code, the corresponding use of compiler