资源列表
ISP1362
- Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序
FPGA_website
- FPGA开发相关的国内外经典网站，有许多值得参考的设计和开源的IP核-FPGA development at home and abroad classic website, there is much reference design and open source IP core
EDA
- 福州大学EDA实验代码,其中包含电子琴,DA转换器,时钟显示器等
zffsq
- 此文是一个完整的字符发生器的设计及设置,文中有完整的vhdl代码及原理图.-This article is a complete character generator design and installation, a complete text of the code and vhdl diagram.
uart
- M_UART 介绍了通用异步收发器（UART）的原理，并以可编程逻辑器件FPGA为核心控制部件，基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试，该设计完全达到了设计要求。
tt
- 这是一个VHDL硬件描述语言所写的一个程序，希望通过仿真然后再看输出结果！-This is a VHDL hardware descr iption language written by a program, and hopes that the results of simulation and then look at the output!
fft4096_8192
- 基于基2的并行4096，8192深度的FFT源代码verilog-Based on radix-2 FFT parallel 4096,8192 depth verilog source code
ddr_verilog
- verilog HDL语言实现在FPGA上控制DDR的逻辑，方法简单易懂，适合新手参考-Verilog HDL language on FPGA control DDR logical, simple to understand for novice reference
controll
- LED控制器 有流水 渐变 等效果。调试通过-LED controller water gradient effects. Debugging
vliw
- vliw processor core vhdl files compiled by myself partly and through the help of net resources.
mux21a
- 应用QuartusII 完成基本组合电路设计-The application QuartusII completion of basic combinational circuit design
mul-function
- verilog编程，调用function实现乘法-verilog programming, call the function to achieve multiplication