资源列表
Arbi
- this the code for arbiters used for master and slave foermat-this is the code for arbiters used for master and slave foermat
adder-4
- 4 位加法器实现4个二进制位的相加 方便快捷-4-bit adder 4 binary bits adding quick and easy
fsk1
- 实现部分搭建FSK调制系统，包括分频，用busmux调制。-Achieve some of structures FSK modulation system
frequency-and--fft
- 包含频谱分析器中的频率采样部分，FFT倒序部分的NIOSII程序。-Contains the frequency sampling part of the spectrum analyzer, FFT the reverse order part NIOSII of the program.
Lab1
- DE2-70七段数码管代码点亮最后一个数码管其它数码管关闭-DE2-70 seven-segment LED
LCD_1602
- verilog lcd1602模块代码，只要往里面输入数据即可显示。-The verilog lcd1602 module code, as long as it is entered, input data can be displayed.
LED_display
- verilog 优化后的LED数码管显示模块，两种写法的比较。-verilog optimized LED digital display module, two written comparison.
clock
- 运用vhdl编写时钟，显示时间，具有基本的功能 -VHDL write clock, display time, basic functions
clock
- 闹钟 运用quartus2软件编写程序，具有调整时间，设置闹钟，整点报时等功能，将整个工程打包了-Alarm Clock using quartus2 software programming, adjust the time, set the alarm, the whole point timekeeping function, the whole project package
iic_v2_00_a
- 基于赛林思FPGA的IIC接口设计，支持主机、从机、多主机通信的总线特性，包括datasheet，C语言源代码。-Sailin Si FPGA-based IIC interface design to support the host from the machine, multi-master communication bus features, including the datasheet, C language source code.
ser_to_4per
- 实现了数据的串并转换，由串码转换为4位并行码，代码用Verilog编写，并经过了Quartus的仿真-Data string and conversion, by the string of code is converted to 4-bit parallel code, the code in Verilog, and after the Quartus simulation
Lab_01_demux
- ITS THE DEMUX OF 4 BIT WRITTEN IN VHDL BASED ON DIGILENT XYLINX 14.2