资源列表
tequantongxuejiaocheng1
- 本教程是特权同学写的里面包含了FPGA设计中一些经验的分享，有基础的可以看看。-This tutorial is privileged students to write which contains some experience to share, based FPGA design.
verilog_rs232_rx_tx
- fpga中verilog实现的rs232串口收发逻辑，基础入门，参考学习串口收发-FPGA in Verilog implementation RS232 serial port transceiver logic, based on entry, refer to the study serial transceiver
FPGA_I2C_Verilog
- fpga上用verilog HDL实现的I2C协议，逻辑编写清晰正确，值得新手借鉴-FPGA on the use the verilog HDL implementation of the I2C protocol, logical write clear and correct, worth novice reference
ddr_verilog
- verilog HDL语言实现在FPGA上控制DDR的逻辑，方法简单易懂，适合新手参考-Verilog HDL language on FPGA control DDR logical, simple to understand for novice reference
ddr_kongzhiqi
- fpga上用verilog HDL实现的ddr控制器，简单易懂，适合新手参考-FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
ChipScope_use
- xilinx chipscope的实用教程，步骤有图，一步步学习，简单实用-Xilinx chipscope practical tutorial, step diagram, a step-by-step learning simple and practical
VERILOG-HDL-Study
- verilog HDL语言学习，讲解十分详细，初学提高都有帮助-Verilog HDL language learning, on the very detailed, beginner improve have helped
FIFO
- 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
LAB3
- THAT IS SOLUTION FOR THE LAB OF DSD LAB 3
lightgc
- verilog code for guide light
smgxssm
- 利用FPGA控制数码管，实现7位数码管的动态显示功能-The use of FPGA to control the digital 7 digital tube dynamic display function
Verilog-UART
- 功能：UART串口通讯实信实验 描述：本程序共四个模块 模块1：接收数据的波特率发生模块，接收模块在接收到下降沿时，通过标志位启 动该模块的波特率计数器，并在计数中返回一个采样标志位给接受模块， 通知接收模块采样； ---------------------------------------------------------------------- 模块2：数据接收模块，该模块一旦监测到数据输入端有下降沿，就立即启动波 特率（标志位置1），并使