资源列表
rs_decoder204_188
- RS译码的Verilog实现，用的是改进的BM算法，已在QuautusII9.0上调试通过-rs decoder verilog
sodamachine
- 刚做完的一个实验，传上来分享一下 写的一般，请见谅 原题是麻省理工的一道EDA设计题：设计一个自动售货机系统，卖soda水的，只能投进三种硬币，要正确的找回钱 数。 （1）用到有限状态机；（2）用VHDL编程 -Just finished an experiment, transfer up to share writing in general, please forgive the original question is a Massachusetts Institute of T
pingpongball
- 利用VHDL语言显示VGA图像，直接输入到CRT-Using VHDL language display VGA images directly into the CRT
PULSE
- 这是一个将6组并行数据串行输出的VHDL源码，配合外部电路可以输出正负脉冲，还附有逻辑图哦。-This is a group of parallel data to serial output 6 of the VHDL source code, with the external circuit can output positive and negative pulses, also with a logic diagram oh.
vhdl
- FPGA设计应用培训VHDL－RedLogic.pdf-Application of FPGA design training VHDL-RedLogic.pdf
T1-add-strobe
- TI DaVinci cpld sources
Gratingthefoursegmentsandthedefensetothecircuit.ra
- 光栅尺的四细分和辩向电路,里面有样图可以之间看到-Grating the four segments and the defense to the circuit, which has kind of map can be seen between
booth_mult
- VHDL code for Booth multiplier for 32bit input
clock
- 用Verilog写的数字钟，用于单片机上实现-verilog
VHDL-for-FPGA
- 非常具体实用的VHDL程序，可以直接用。非常适合新手使用。-Very specific and practical VHDL program can be directly used. Very suitable for novices to use.
DECODE
- 利用状态机将并口发送的六组8位数据转换成串行正负脉冲数据发出。-Using the state machine will send the six groups of parallel data into serial 8-bit data to issue positive and negative pulses.
CLK_DIV_N
- 对输入的时钟进行分频输出:输出频率＝ 输入频率/(2*N+2-Of the input clock frequency output: Output frequency = Input frequency/(2* N+2