资源列表
44_reg_counter
- 用VHDL写的计数器程序例子,
stc
- stc设计与实现,也即时间增益放大的设计,工程中有很多用处。-the implention of stc
can
- can总线的verilog设计与实现,很好的资料哦-the implention of can bus with verilog
ref-sdr-sdram-verilog
- sdram的verilog 建模参考设计,希望有所帮助-sdram and verilog implent
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
shuzitiaozhijietiaoqi
- 数字调制解调器 数字调制解调器 -Digital Modem
vhdl
- 这是基于VHDL设计的抢答器 通过抢答者的指示灯显示、数码显示和警示显示等手段指示出第一抢答者-This is based on VHDL design Responder Responder' s light show through a digital display and warning display means of the First Responder who directed
flf
- 乘法器的计算方法和程序,适合新手学习语法,直接的代码-mulcon
lab1-lab3
- XILINX EDK中三个简单的实例!有PDF详细说明-XILINX EDK in three simple examples! A PDF details
Xilinx_3SE_Starter_Serial_Flash_v91
- sparntan 3e中基于串行flash的读写操作-sparntan 3e serial flash-based reading and writing
