资源列表
test_wuline
- 用 verilog语言实现直线的显示与反走样，用的是wu算法，适用于fpga实现-The Verilog language line display with anti-aliasing, wu algorithm, suitable for fpga implementation
counter-0-9999-on-DE1
- Hello its simple counter for DE1 boards
CPU8bit
- 复旦大学 计算机体系结构实验 8位cpu-8bit cpu
te_copy
- 利用verilog编写的频率计，测量信号通过管脚输入，8个七段管显示频率，可以实现1-50M频率的精确测量-A frequency indicator based on verilog HDL, measured signal connect the chip by the input pin and display the result on the seven segment.It could realize the frequency measurement accurately.
FPGA-FIFO-VHDL
- 这是一个基于FPGA的异步FIFO设计，利用的VHDL硬件描述语言，内容分析清楚，附带完整代码-This is an FPGA-based asynchronous FIFO design, the use of VHDL hardware descr iption language, content analysis, with complete code
fifo
- 本文档是一个异步FIFO设计的完整工程，利用modelsim仿真软件，分不同的模块-This document is the complete works of an asynchronous FIFO design, the use of the modelsim simulation software, divided into different modules
VHDL-TESTBENCH
- 这是一篇用VHDL编写testbeach测试文件的详细讲解资料，举例讲解详细易懂，很实用-This is a VHDL explain in detail the information writing testbeach test file, for example, to explain in detail to understand, it is practical
DDS
- 在FPGA里面实现DDS的功能，输出正弦、三角波、方波、FSK/ASK/BPSK调制波等-Inside the FPGA realization of DDS function, the output sine, triangle wave, square wave, FSK/ASK/BPSK modulation wave
Asynchronous-FIFO-structureadesign
- 异步FIFO结构和FPGA设计，首先介绍异步FIFO的概念、应用及其结构，然后分析实现异步FIFO的难点问题及其解决办法；在传统设计的基础上提出一种新颖的电路结构并对其进行综合仿真和FPGA实现-The asynchronous FIFO structure and FPGA design, first introduced the asynchronous FIFO concept, application, and its structure, and then analyze the as
5.4_AudioFilter
- 基于SystemGenerator的音频滤波器，实现后可以在SPARTAN6中运行。-Based on the audio SystemGenerator filter implemented in SPARTAN6 run.
DDS_FPGA_Materals
- DDS的FPGA设计原理、结构和原代理，包含源代码和ModelSim仿真，是DDS初学者参考的优秀教程，图文并茂，上手容易！-DDS FPGA design principles, the structure and the original agent, including source code and ModelSim simulation，it is an excellent book for greenhand in studying DDS, the book is composed
5.3_AudioWatermarking
- 基于SystemGenerator的音频信号处理，可以成功在FPGA上验证-Based SystemGenerator audio signal processing can be successfully tested in FPGA