资源列表
pcitarget_disconnect_verilog
- This design shows how to implement a disconnect of a pci target instantiation of Altera s pci megafunction
MP3_VHDL
- Complete implementation of MP3 decoder in VHDL.
fsk3_2_2
- 用Simulink搭建的2fsk调制解调系统-Simulink structures 2fsk with modulation and demodulation of the communication system
axi_master_latest.tar
- RobustVerilog generic AXI master stub源码，包括文档说明-RobustVerilog generic AXI master stub
fir filter design
- FIR FILTER DESIGN IN VERILOG ON FPGA
序列检测器
- 本例子为一个序列检测器的程序，序列为：110010010000100101００，检测的序列为10010(This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010)
xapp502配置例程
- FPGA配置例程，VHDL语言，使用CPLD对FPGA进行配置(The FPGA configuration routine, VHDL language, using CPLD on the FPGA configuration)
VHDL程序
- 利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)
OSVersion
- os version Descr iption
Mux41a
- Basys3 4选一数据选择器代码，初级者学习，在板子上试验过，没问题。(Basys3 4 select a data selector code)
NEW
- Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua Un
test_div
- 定点除法器程序，分为被除数大于除数和除数大于被除数两种情况