资源列表
FIFO_exp
- 一个关于如何使用 xilinx FIFO 的经验，非常值得借鉴-a PFF report about how to use FIFO core
modsim
- modsim仿真必备，可以帮助你解决很多你对软件不熟悉的问题！
DDR_CTRL
- DDR Verilog 控制器，quartus 10.1工程。适用Altera Cyclone® III starter board-DDR control quatrus 10.1，Altera Cyclone® III starter board
verilog-experience-for-beginners
- VerilogHDL语言的设计经验，适合初学者入门学习，包含了Verilog编写时需要注意的很多方面，很有参考价值。-VerilogHDL language of design experience, suitable for beginners to learn, including the need to pay attention when writing Verilog many aspects of great reference value.
counter_four
- 模拟了半加器和全加器的vhdl语言源码。-model half add and full add mechine vhdl code
verilog_经验(适合初学者)
- verilog初学者学习经验.适合菜鸟.(Verilog beginner's learning experience. Suitable for rookie.)
UART
- 本人用verilog编写的UART协议，经测试可用。(I am prepared to use verilog UART protocol, the test is available.)
lcd_12864
- FPGA控制12864液晶显示、驱动，字符，汉字，用Verilog语言写的，经本人调试仿真过，绝对没问题-FPGA control 12864 LCD driver, characters, Chinese characters, written using Verilog language, I debug simulation absolutely no problem
00ec9231-3ad2-48d5-a4ae-b0b4b28125a5
- 这是vga实验的源代码，仿真实验通过，并通过下载板子上与led连接实现，希望大家共同努力-This is a vga experiment source code, through simulation, and led by downloading and connection to the board, hope we work together
Task06_DSP48A1
- 基于Xilinx Spartan 6 FPGA的DSP48A1 slice 的使用实例-DSP48A1 slice Use examples Base of Xilinx Spartan 6 FPGA
my_sd_vga_test
- 基于FPGA的SD卡控制器，从SD卡中读取图像信息，并通过VGA显示-SD card controller based on FPGA, Read the SD card information, and through the VGA display
ADigCLK
- 用VHDL编写的一个数字钟。该模块是顶层模块，用VHDL例化语句例化各个子模块并组装成一个完整的数字钟。与我的其它8个模块配套构成一个数字钟。 -A digital clock programmed with VHDL.This module is the top-level module, it utilizes the Component instantiation of VHDL to incorporate all submodules into a complete digital