资源列表
PS2_jianpanshibie_FPGA
- 实现了PS2接口的主键盘和小键盘的识别，采用第二套键盘译码表，如果你想使用第一套或者第二套键盘译码，只需做少量的修改就可以实现。只要稍加修改就可以实现你所希望的功能，此程序只实现了LCD灯的控制。-PS2 interface implements the main keyboard and keypad recognition, using the second set of keyboard decoding table, if you want to use the first set or
RSA
- programme qui decrit l algorithme de chiffremment RSA
SpecmanEliteTutor
- SPECMAN ELITE CODE TUTOR for learning Platform to verify VHDL and VERILOG Codes
SegScanDisp
- 基于VerilogHDL编写的7段数码显示管动态显示实验开发程序。-7 VerilogHDL prepared based on the digital display tube dynamic display experiment development process.
Intel-Atom-Z5xx-TI-power
- 用于 Intel Atom Z510、Z530 和 Z5xx 平台的 TI 电源解决方案.rar-For the Intel Atom Z510, Z530 and Z5xx TI Power Solutions platform. Rar
b8bit_adder
- 8位的加法器设计，分4个工程完成的，用的是Quartus II软件。-eight of the adder design, four hours to complete the project, using the Quartus II software.
aes-128_pipelined_encryption
- AES 加密算法 基于流水线设计 成熟IP core-AES encryption algorithm based on pipeline design mature IP core
CCD_drive
- TCD1304 CCD 驱动 AD转 USB2.0传输(This code based on verilog language, worked on EP1C3T144 FPGA chip, developed on Quartus II 12.0 . The ccd's data transformed by USB2.0 after amplified and AD confromed.)
maxII_verilog_i2c
- verilog语言在maxII系列芯片上实现iic功能
fifo
- 这是一个基于FPGA的fifo程序，使用环境为Quartusruan软件，已经过实验，成功。-This is an FPGA-based fifo program, the use of the environment as Quartusruan software has been experimental, successful.
pipeline
- 用流水线构成的串行八位加法器，可以输出进位级联-With a line consisting of eight serial adder, can output binary cascade
VGA_v
- 基于 FPGA 的VGA显示控制器设计（采用Verilog 语言） 控制VGA显示模块 VGA_HS,VGA_VS1,VGA_BLANK时序的发生器。包括测试程序 采用ALTERA Cyclone II系列芯片EP2C8Q208C8N芯片测试成功。-module VGA(CLK_50,RST_N,VGA_HS,VGA_VS1,VGA_BLANK, VGA_CLK,VGA_SYNC,VGA_R,VGA_G,VGA_B) input