资源列表
eeprom
- eeprom的Verilog HDL源代码，含eeprom的读写！Quartus II5.0平台测试通过！
EPM240Prj.rar
- 这是一个verilog HDL 语言的例子，在CPLD器件EPM240上实现了 RS232协议、按键处理、LED数码管显示和每秒加1数码显示。使用quartus ii 7.0 以上打开.,This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plu
SM2100
- 基于CPLD的增量式光电码盘SOPC使用手册-CPLD-based incremental photoelectric encoder SOPC Manual
VHDLrsjiemaqi
- 设计中国移动多媒体广播中的RS解码器,该RS码采用码长为240字节的RS(240, K)截短码-RS decoder design in China Mobile Multimedia Broadcasting
RS-decoder
- RS 解码器主要包括以下5 个主要部分：伴随式计算、计算错误位置和错误值多项式、 钱搜索计算错误位置、福尼算法计算错误值和纠正解码输出。-RS decoder includes the following five main parts: With style, calculated error location and error value polynomial, Calculated error location search of money
key_led
- 简易计算器的键盘和LED显示，很简单，但也可以说很复杂-Simple calculator keyboard and LED display, very simple, but can also be said very complicated
AES
- AES implementation in VHDL@!
SDRAM
- 用FPGA实现对sdram读写的源代码，芯片用的是Altera公司的，需要的同学可以看看！-FPGA realization of sdram read and write the source code, the chip using Altera' s, students need to take a look!
扰码器Verilog
- 实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)
three
- .实十位加法计数器程序，要求从0-9进行计数2验设计(The ten bit adder counter program requires 0-9 to count from 2.experimental design)
ml405_schematics
- Xilinx Virtex 4 ML405开发平台的原理图 设置引脚文件的时候可以用到
add_tree_mult
- ＦＰＧＡ的ｖｒｉｌｏｇ ＨＤＬ代码，树型乘法器-FPGA-vrilog HDL code, tree multiplier