资源列表
VerilogHDL-Code-Formatter-V1.2
- 这是一款Verilog代码格式化工具. 用于代码格式美化。您可以根据自己的VerilogHDL格式需求，在右侧控制面板中进行控制，左侧即时显示出当前设置的格式。是一款好用的VerilogHDL代码格式工具。-Format landscaping. According to their own VerilogHDL format requirements, you can in the right side of the control panel to control the real-time
combine11
- traffic light system,written in VHDL language.It has already been tested.But you may take sometime to figure it out
reg_add
- 在quartus中仿真通过的移位加程序的vhdl代码
at7_ex01
- 8个LED执行流水灯。流水灯依次循环点亮。基于vivado平台编写的Verilog代码(The 8 LED executes the flow light. The flow light is turned on and out in turn. Verilog code based on vivado platform)
SPA
- 首先介绍了LDPC码的校验矩阵和其因子表示方法，然后利用二分图对和积解码算法进行了详细的描述，最后给出了信度传播概率译码算法详细步骤，并对关键公式作了证明-This paper,first introduces the check matrix and the factor graph of LDPC,then describes the sum-product algorithm by using the factor graph,and finally presents the deta
Multifunction-Clock
- 多功能电子钟，实现自动时钟日历的程序，含有时分秒日月年-Multifunction Clock
clock
- 在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间
Constant_PQ_Microgid_matlab
- 逆变器并网发电的主要是逆变器输出正弦波电流的控制技术，要求与电网同频同相的电流，此matlab模型中使用锁相环技术，恒功率控制，LCL滤波器技术使达到并网要求-Constant_PQ_Microgid
shumaguanxianshi8--3yimaqi
- 基于FPGA的数码管显示8--3译码器，经过验证运行了得-FPGA-based digital display 8--3 decoder, a proven run terrible
UART
- 基于FPGA的UART实现 用VHDL编程-The UART-based FPGA using VHDL Programming
BCD_divid_new
- VHDL语言编写的8位BCD除法器，可以实现浮点数计算，只支持正数运算，并用isim进行仿真-VHDL language 8 BCD division, can achieve floating-point calculations, which only supports a positive number arithmetic, and use isim simulation
XO2_RAM
- Lattice XO2系列内部RAM使用源码-Lattice XO2 RAM