资源列表
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
SDRAM-verilog
- SDRAM控制器.用verilog实现SDRAM的读写操作。-sdram coll
lift
- 用VHDL编写的全功能四层电梯控制器-Prepared with a fully functional VHDL four elevator controller. . .
UART
- URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha
udcounter.v
- this program is for 8 bit up counter
lifttttttttttt
- THIS THE SECOND METHOD FOR LIFT CONTROLLER-THIS IS THE SECOND METHOD FOR LIFT CONTROLLER
tcpudp
- Nios2 for enc28j60 use TCP and UDP with arp and IMPC for ping
VHDL
- 通过VHDL语言编写的可以实现预置歌曲，并将其播放出来-VHDL language can be preset songs, and played
vhdl
- 通用寄存器，移位寄存器，简单状态机，直流电机控制器，-General registers, shift register, a simple state machine, DC motor controllers, etc.
forkey
- c语言编写51单片机键盘扫描程序，方便移植到其他的硬件上去
555times
- 此信号发生器可以实现准确地实现信号发生，功能完善-This signal generator can signal to achieve accurate, functional
Sdram_Control_4Port
- verilog 编写的sdram控制代码，很好的参考例子-sdram verilog write control code, a good reference example