资源列表
Sum
- 实现加法器功能的简单verilog代码，可以为初学者提供学习。-Achieve a simple verilog adder function code can provide learning for the beginners.
zr36060.tar
- vhdlsource code for jpegpack
count_16
- 十六进制计数器，还可以，使用VHDL编写的，下载试试吧-Hexadecimal counter, you can also use VHDL written Try now
cekongxitong
- 一个虚拟测控系统，可以采集信号发生器里的信号并对其进行处理（频率计算与fft变化等），可提取数据与保存数据-A virtual control system, can acquire the signal generator signal and its processing (frequency calculations with fft changes, etc.) can extract data and save data
PS2keyboard_verilog
- 本实验利用PS2接口实现了与键盘通信，并将键盘的按键编码通过UART接口上传给PC的超级终端，通过超级终端来观察按键编码是否正确。 -experimental use of the PS2 interface with the keyboard communications, and keyboard buttons coding through UART interface to the PC upload the Super Terminal, Super Terminal throug
systemcmd5_latest.tar
- MD5 Hash Algoritm. Source code VHDL
Descrierea_comenzilor
- Translation of the datasheet of the UC1610 GLCD controller
DM9000A.VerilogHDL
- 用VerilogHDL语言实现的DM9000A控制器的代码,是用FPGA做SOPC的重要组成部分-VerilogHDL language used to achieve code DM9000A controller is the use of FPGA to do an important part of SOPC
IP_COE_Abs2Rel
- 编程辅助软件，将Xilinx ISE 14.x IP核含有的COE文件从绝对路径改成相对路径-Progrmming assisting software, Xilinx ISE 14.x IP core have COE file absolute path change into relative path
10chapter
- 王金明verilog书中第十章的例子 适合初学者-Wang Jinming verilog example Chapter book for beginners
Multi
- A Complete Multicycle CPU Written in Verilog Lang.
lcd-character
- this is for display character on lcd-this is for display character on lcd