资源列表
RUILI
- 均匀相位的瑞利衰落信道matlab仿真程序，并附有详细注释-Uniform phase Rayleigh fading channel matlab simulation program, together with detailed notes
3-8-decoder
- 三八译码器,用Verilog HDL语言描述，包含文件说明以及波形截图-3-8 decoder using Verilog HDL language descr iption, including documentation and waveform capture
8-1-mux
- 八选一数据选择器，Verilog HDL语言描述，包含文件说明和波形截图-8-1 MUX, Verilog HDL language descr iption ， contains the file descr iption and waveform capture
10010sequece-detector
- 序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-Sequence generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
M=15generator
- 模15序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-mod15 generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
voter
- 少数服从多数表决器，Verilog HDL语言描述，包含文件说明和波形截图-Majority voter, Verilog HDL language descr iption, contains the file descr iption and waveform capture
mux4
- 改程序实现的四选一数据选择器的工程，该程序为自己编程，并经过仿真验证此程序正确-Reform program to achieve the four selected a data selector works, the program for their own programming, and through simulation this procedure correctly
ds_test12
- 在Verilog语言下用FPGA驱动DS18B20，带数码管显示，带LED报警，有报警值调整功能。这个是本人调过的，原版调通代码没改的，绝对能跑通。建议用QuatusII全编译后看一下RTL图就能理解程序是怎么工作的。-A Demo of DS18B20 on FPGA.
curriculum_design_v2
- 课程设计，数字频率计源代码，用Verilog HDL写的-Curriculum design, digital frequency meter source code, written using Verilog HDL
BlazeNoC_QoS-master
- BlazeNoC_QoS：支持QoS的可重配置片上网络路由，有很高的性能。此代码包括完整的Xilinx ISE的工程，可以很方便地修改和移植。-BlazeNoC_QoS: QoS-reconfigurable chip network routing, a high performance. This code includes a complete Xilinx ISE project, can be easily modified and transplantation.
Virtex-5--user-manuals-chineses
- xilinx virtex-5 中文用户手册 介绍了virtex5 的内部结构 功能和使用示例 完整清晰 -Chinese virtex5 user manual describes the function and use of the internal structure of an example of complete and clear
VHDL
- virtex-5 库声明代码 VHDL版本 完整的原语示例代码-virtex-5 library declaration versions of the complete VHDL code sample code primitives