资源列表
EX8
- 累计进位加法器和超前进位加法器，数字逻辑课程作业-Cumulative carry lookahead adder and adder, digital logic course work
vhdl
- 通信系统中，HDB3码使用VHDL语言的仿真，实用性强。-Communication systems, HDB3 code simulation using VHDL language, and practical.
Synchronous_Design-of-huawei
- 华为公司在进行FPGA/CPLD设计时针对毛刺干扰及时序匹配所采取的同步化策略-Huawei making FPGA/CPLD design and timing match against glitch synchronization strategies adopted
LED-xianshi---yimaqi
- 7段LED显示译码器的设计 采用文本输入设计方法，通过编写VHDL语言程序，完成7段LED显示译码器的设计并进行时序仿真。 2、 设计完成后生成一个元件，以供更高层次的设计调用。 -7-segment LED display decoder design using text input design method, by writing VHDL language program, complete the seven-segment LED display decoder desig
series_rxd_timing
- 接收异步串口数据，将数据写到接收fifo中，可设置超时来接收多字节数据，当设置超时时间内未出现数据，ready信号有效，表示接收完整数据包，可从fifo中读取数据。-Receive asynchronous serial data, the data is written to the receiving fifo, you can set the timeout to receive multi-byte data, set the timeout period when the data d
UltraSensor-Vram-V8
- Verilog语言编写的FPGA程序，有串口收发引擎代码，AD初始化采集代码,键盘扫描代码-FPGA Verilog language program, a serial port transceiver engine code, AD initialization acquisition code, the keyboard scan codes
RAM_VHDL
- 用VHDL描述了一个32KBit的独立的读写时钟、使能、地址的双口RAM，-VHDL descr iption of a 32KBit with independent read and write clock, enable, address the dual-port RAM,
MULTIPLICATER_AND_ADDER
- 本程序描述了实现函数y=ax+b（a和b 都为小于1的8bit小数）的硬件电路描述，最后得到的结果只取了整数部分，为8 bit输出，并且对小数部分四舍五入了。-This procedure describes the implementation function y = ax+b (a and b are less than 1 8bit decimal) descr iption of the hardware circuit, the final result just take the
modelsim-run-one-step--Error-
- 用modesim仿真的时候会出现只运行了一步就不动了，显示"# ** Error: (vsim-3601) Iteration limit reached at time 0 ps."的解决方法。-With modesim simulation run only when there will be a step not move, display " #** Error: (vsim-3601) Iteration limit reached at time 0 ps." S
CS5361_DAT
- CS5361 ADC 驱动程序,其中还有时钟部分,这里是数据采集部分. 使用VerilogHDL编写,在Libero中编译,使用Actel芯片测试通过.-CS5361 ADC drivers, of which there are clock parts, here is the data collection using VerilogHDL written, compiled in Libero using Actel chip test.
keshe
- 也许是一个比较有用的数码骰子。。经过随机数然后进行数码管显示-Perhaps a more useful digital dice. . After a random number and then the digital display
lab4_project
- lab4中基于ISE的lab4实验的程序源代码，这里使用的是ISE13.4的版本-lab4 in ISE-based lab4 experimental program source code, here is the version ISE13.4