资源列表
Freq_Count_Test-8.15
- Verlag代码，频率计，计算输入触发信号的频率，频率=工作时钟/计数结果。-Verlag code, frequency meter, calculate the input trigger signal frequency, frequency = operating clock/count the results.
LAB2
- 一步 学ZedBoard & Zynq-STEP BY STEP STUDY ZedBoard & Zynq
Lab3
- 一步 学ZedBoard & Zynq-STEP BY STEP STUDY ZedBoard & Zynq
moshuzhuanhuan1111
- 模数转换，将8路并行的数据缓存在FIFO中，再输出。通过时序控制A/D芯片的采集速度，和ARM板的接收速度。-Analog-to-digital conversion, eight road parallel data cached in FIFO, and output. By sequential control of A/D chip acquisition speed, and ARM board receives the speed.
WISHBONE_conmax
- 很详细的wishbone总线学习借鉴代码和文档-Very detailed wishbone bus to learn from the code and documentation
counter_99
- XINLIX soprtan3 源码，实现计数器功能，可加减计数并在数码管上显示，可调节计数间隔。-XINLIX soprtan3 source code to achieve the counter function, counting and addition and subtraction on the digital display, adjustable counting interval.
output_10014537
- XINLIX SPORTAN3 FPGA 可在数码管上显示滚动的数字，可自由设置，程序设计时钟分频等-XINLIX SPORTAN3 FPGA in the digital tube display scroll figures can be set free, program design clock divider, etc.
tswc_state
- XILINX SPORTAN3 实现状态机功能，状态切换，可以改变状态切换的时间。 -XILINX SPORTAN3 implement state machine function, state switch, the switching time may be changed.
weiji
- 基于FPGA的UART设计，fpga简单的波特率发生器设计-FPGA-based UART design, fpga design simple baud rate generator
FPGA6_LCDaUART
- 基于FPGA Verilog LCD显示串口数据-Based on the FPGA Verilog LCD display serial data
FPGA7_UART
- 基于FPGA Verilog UART接口数据传输-Based on the FPGA Verilog UART interface data transfer
FPGA9_VGAaUART
- 基于FPGA Verilog VGA 显示 UART 数据-Based on the FPGA Verilog VGA display UART data