资源列表
C_ADDSUB_V1_0
- 针对xilinx器件的重要库文件，能够加快基于xilinx器件的工程开发，提高系统的性能。-For important library xilinx devices, to accelerate project development based on xilinx devices to improve system performance.
C_COMPARE_V1_0
- 针对Xilinx器件的关键库文件，该库文件实现了比较器的功能，能够加快项目的进度！-The key database file for Xilinx devices, the library implements the comparator function, to expedite the progress of the project!
aes_-vhdl
- aes encription coding in vhdl language
AES128
- AES128 encription vhdl code
t3_sdram
- 完成sdram读写操作，并附有测试脚本文件，已通过后仿验证。该程序主要包括上电初始化模块，刷新模块，读、写模块等，并采用FSM控制所有模块，完成数据的读写操作-Sdram read and write operations to complete, with a test scr ipt file has been verified through simulation. The program includes power-on initialization module, refresh m
pg054-7series-pcie
- 赛灵思 7系列pcie设计，官方参考资料-xilinx 7 series FPGA PCIe design， reference
sin
- 产生正弦波 相位，频率，精度可调，实在没得写，凑字数-Generates a sine wave phase, frequency, precision adjustable, it did not have to write, Minato words
ac701-pcie-rdf0225-2013.2-c
- 赛灵思7系列开发板ac701，PCIE参考设计，VHDL/Verilog，开发环境Vivado-xilinx 7 series design Kit AC701 PCIe reference design. VHDL/Verilog, design environment Vivado
mux16
- 基于FPGA的verilog编写的乘法器-FPGA-based multiplier verilog prepared
AES_verilog
- 对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
Pdf
- Barrel Shifter VerilogHDL code
Barrel Shifter
- Barrel Shifter Verilog Code