资源列表
clock
- 用FPGA制作的电子时钟，程序简洁，时钟走时精准，带整点报时功能-FPGA with the production of electronic clock, the procedure is simple and accurate travel time clock, time zone function of the whole point
crack_dsp_builder_701
- dspbuilder7.0的破解文件，为开发人员必须安装MATLAB7.0以上的版本-the crack dspbuilder7.0 document MATLAB7.0 developers must install the version of the above
Serializer
- Serializer - UART Transmitter and Receiver Complete Project with waveform file-Serializer- UART Transmitter and Receiver Complete Project with waveform file
UpDownCounter
- 8-Bit Up Down Counter Verilog Code
AdderSubtractor
- 4-Bit Adder Subtractor Verilog Code. (Complete project)
Receiver
- UART Receiver Verilog Code
Transmitter
- UART Transmitter Verilog Code
qts_qii54004
- ALtera Corpartion handbook for SOPC builder
source
- 王金明：《Verilog HDL 程序设计教程》，包含很多基本例程，还有一些综合应用例程-Wang Jinming: " Verilog HDL Programming Guide" , contains many of the basic routines, and some integrated application routines
n2cpu_nii5v1
- This the Quartus Handbook-This is the Quartus Handbook
Digital_video
- 配合DSP做的例子，前段视频采集和转换后， 通过切换SRAM中的数据到DPS后端处理和FPGA采集操作，具有 一般通用性，更重要的是测试代码丰富，加深理解-DSP to do with the example of the preceding video capture and conversion, the SRAM through the switch to DPS data processing and FPGA back-end collection operation, a g
Spartan3VGATest
- This VGA test will draw a single color page and change color every one second. VGA resolution is 640x480 @25 MHZ 8 colors