资源列表
mydds_rom
- 自己在参加altera NIOSii 软核设计大赛时编写的一个ip核，用于产生频率可调的正弦波-Their participation in the design of soft-core altera NIOSii the preparation of a competition when nuclear ip, used to generate the sine wave frequency adjustable
Count
- 基于FPGA图形方法的同步模231计数器（设秒脉冲已给） -Graphical method based on the synchronous FPGA module 231 counter (pulse has been set up to)
seven
- 基于FPGA图形方法的七人抢答器-FPGA-based graphical methods of Seven Figure Answer
ISPcode
- 基于xs300an开发板编写的一系列ISP程序，对与学习FPGA的编程控制有一点帮助-Xs300an development board based on a series of ISP preparation procedures, FPGA programming and learning to control a little help
DEMUX
- Demultiplexor vhdl code
Register8bits
- Register 8 bits VHDL code
divisor
- Time divisor vhdl code
COD_MANCHESTER
- Manchester Coding vhdl code
Counter8
- Counter 8 bits Vhdl Code
CRC32
- CRC32 Vhdl component
VHDL
- 基于FPGA交通灯控制VHDL源代码,东西，南北，主干，支干-FPGA-based control of traffic lights VHDL source code
4_Bit_Alu_vhdl
- Complete VHDL Code for a 4 BIT ALU PROJECT