资源列表
tristate
- VHDL code for a full adder and n bit full adder a tri state buffer and a flip flop
BCD_adder
- VHDL code for a one bit comparator and an n bit register and a BCD adder
stoplight
- VHDL code for a 4 state stop light with police control input
mux_reg
- VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
Desktop
- VHDL code for 16 byte ROM & n bit comparator & a full adder
FIFO
- VHDL code for first in first out register
ram32b
- VHDL code for 32 byte RAM
edge_detection
- edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
vhdl_mult
- hardware multiplier in VHDL
FPGA_Sistem_Embeded
- This is File from Lab ITS Surabaya
89S52heFPGA
- 关于verilog 和8052系列单片机的C语言程序 用于点阵型12864显示-fhds pd[dsfkjjklsdff
VGAgen
- vga generation, genearting vga using fpga or any others resources