资源列表
wishbone
- wishbone接口的设计，在交换机和MAC之间建立wishbone接口-the wishbone interface design, wishbone interface between the switch and MAC
ex2
- 七段码 练习使用 verilog 源代码-Seven-segment code practice using verilog source code
Verilog-HDL-Digital-Design
- Verilog HDL 数字设计与综合 夏宇闻-Verilog HDL Digital Design and Xia Wen
sdram_mdl
- SDRAM VERILOG源代码 控制读写-SDRAM VERILOG source code control read and write
VHDL-program
- VHDL实验程序。需要的可以在此基础上修改。-Program VHDL experiment. Need can be modified on this basis.
HappyBirthday.v
- 基于Virtex-5的Happy Birthday程序 Verilog-Virtex-5-based the Happy Birthday procedures Verilog
priority_data_encoder_vhd.zip
- priority data encoder,priority data encoder
serial_in_vhd_data_conversion.
- signal data conversion,signal data conversion
edge_detect
- 采用VHDL语言编写的边缘检测源代码，在xilinx公司的spatan-3an的仿真版上验证无误，供初学者学习-Edge detection using VHDL language source code, verification, simulation version of the company spatan-3an xilinx for beginners to learn
grlib-gpl-1.1.0-b4113
- gaisler开发一些免费可以使用的ip集合，我们很多常用的ip代码都可以在其中找到。-gaisler developers can use for free ip collection, many of us used the ip code where you can find.
first
- 3-8译码器：输入变量为三个A,B,C，输出变量有8个，即Y0~Y7。 G1,G2A,G2B为选通输入，仅当G1=1, G2A=0, G2B=0时，译码器能够正确输出，否则，译码器输出无效，Y0~Y7均为高电平“11111111”。 -The 3-8 decoder: input variables for the three A, B, C, the output variables are eight, i.e. the Y0 ~~ Y7. G1, G2A, G2B strobe
sipo_vhd.zip
- serial in parallel out using vhdl,serial in parallel out using vhdl