资源列表
VHDL_LAPS
- 简化LAPS协议，对发送的数据包进行封装、传输和接收，，包含FCS是对整个LAPS帧进行CRC校验。-Simplify LAPS protocol, encapsulation, transmission, and receiving the transmitted data packet, containing FCS is performed on the entire LAPS frame CRC.
Virtex-5_FPGA_yonghuzhinan
- Virtex-5相关文档，适合于开发初期的了解工作。-Virtex-5 document, suitable for the development of the understanding of the early work.
DDS
- 一个DDS的程序，很有用，可以产生频率可控的正弦波-A DDS program is useful, can produce controllable frequency sine wave
ultimate_crc_latest.tar
- CRC循环校验源代码，来源于OPENCOREs,用于数字电路中的错误检验。-CRC Cyclic check source code from the OPENCOREs, the error checking used in the digital circuit.
stepmotornios
- Altera SOPC系统和Nios II处理器实现的一个简单的步进电机驱动系统。
pipelined_reconfig_multiplier
- parallel pipeline reconfigurable multiplier
SRAM_16Bit_512K
- terasic的DM9000A模块源码，使用nios2做以太网应用的应该会用到-terasic the DM9000A module source, use nios2 do Ethernet applications should be used
dds
- 是vhdl语言写的dds的部分代码，留下来，方便以后查看-The vhdl language written dds part of the code , to stay , convenient View
fp-im-of
- its abt in vhdl ,frequency estiator
Multi
- A Complete Multicycle CPU Written in Verilog Lang.
dds
- 可以完成直接频率合成器功能的VHDL代码-VHDL code which can complete the function of Direct frequency synthesizer.
Foreign-classic-Verilog-code
- 国外经典verilog代码 养成良好的代码风格-Foreign classic Verilog code