资源列表
lbq3
- 滤波器的verilog代码 主要是对算法的折叠 有原先的4个加法器四个乘法器变成2个加法器两个乘法器-Filter verilog code folding algorithm 4 adder four multipliers into two adders and two multipliers
design
- static timing analysis and timing paths
arm-fpga.rar
- arm fpga 通讯驱动代码 arm fpga 通讯驱动代码,arm fpga comunicate
pci
- PCI硬核源代码,支持33.3M的时钟频率,支持IO模式和内存模式的PCI操作-PCI operation of the the PCI hard core source code, support 33.3M clock frequency to support IO mode and memory mode
EDAjiaotong
- EDA交通灯 红黄绿左拐，四个等，不同时间，还有计时器-EDA red yellow and green traffic lights turn left, four different times, there is a timer
simplepwm
- quartusII调试，简单的pwm信号输出，FPGA初学者入门程序，高手勿进-quartusII debugging, not into simple pwm signal output FPGA beginner program, master
DDS
- 这是一个用EP2C5T144的FPGA制作的DDS信号发生器，输出信号波形可变，幅度可调，缺点是信号频率略低，带有电路图-This is a used EP2C5T144 FPGA produced DDS signal generator, the output signal waveform variable adjustable amplitude, the disadvantage is that the signal frequency is slightly lower, with
Pipeline-and-FIFO
- Pipeline and FIFO的FPGA设计-Pipeline and FIFO FPGA design
Key_Xiaodou_Delay
- Verilog语言，Quartus II开发环境，按键延时消抖IP。-Verilog language, Quartus II development environment, key delay shake away IP.
decoder83
- 一个83译码器，使用VRILOG写的，对初学者很有用-A 83 decoder
shizhongfinal
- 通过按键控制的数字钟，verilog代码-a diagil clock design by verilog
VHDL_FIR
- VHDL设计的14阶FIR滤波器，根据已给出滤波器系数以及验证程序，选用Altera的EP2S60F484C3器件进行设计。-VHDL design of the 14-order FIR filter design, according to the filter coefficients as well as the verification process has been given the EP2S60F484C3 selected Altera devices.