资源列表
verilog-program
- 国外经典verilog程序集锦，含有从最简单的定时器创建到复杂逻辑的实现。-Classic Collection verilog program abroad, with the timer created from the most simple to complex logic.
1553_enc_dec.rar
- 1553B编解码程序 verilog 描述,1553B codec procedures described in verilog
h.264
- 包含h.264的包括帧内、帧间、变换编码、熵编码的vhdl源程序-Contains the vhdl source h.264 frame, frame, transform coding, entropy coding
SdpCtrlSimPrj
- 一个对芯片进行软件解锁的仿真工程，可以在Modelsim环境下仿真运行，可作为学习Verilog和仿真的朋友的一个很好的例子-One pair of chip engineering simulation software unlock, you can run in Modelsim simulation environment, simulation can be used as learning Verilog and friends a good example
divide
- divide模块，实现除法功能。该module是用Verilog编写的，压缩包里包括了设计程序以及测试程序（testbench）。-divide module, the division function. The module is written in Verilog, compression bag, including the design process and testing process Sequence (testbench).
gk
- a verilog code of 3 input and gate.
Matlab_Codes
- Matlab for Digital Signal Processing
DATA_Scramble
- 扰码器的FPGA实现，选择的扰码器规格为15位移位寄存器。(FPGA scrambler, scrambler specifications for a 15 bit shift register.)
major1
- code for inverting an image in verilog
AHB2-master
- AMBA AHB 2.0 VIP in SystemVerilog UVM
fpga 程序
- crc 校验
crc_16
- 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.