资源列表
11
- 华为FPGA设计流程指南 华为FPGA设计流程指南-FPGA Design Flow Guide Huawei Huawei FPGA Design Flow Guide
URAT-
- 异步串行通信接口UART的VHDL程序实现-Asynchronous serial communication interface UART VHDL program realization
CPU_VHDL
- 一个TISC的模拟cpu代码，一共有200多行，不过麻雀虽小，却五脏俱全，而且作者对每行代码都做了详细的说明，下面仔细的分析一下。-Simulation of a cpu code TISC, a total of more than 200 lines, but the sparrow is small, it is a fully-equipped, and lines of code for each author has done a detailed analysis of the f
fftipcore
- 实现fft的ip核，用vhdl语言实现。-Fft realize the ip nuclear, using VHDL language.
Mc68000
- Mc68000 rtl code Simulation and Synthesis
ADC0804-Driver
- FPGA 本实验是用 驱动 adc0804 这个芯片，由于驱动这个芯片要使用有一定的时序控制，所以本实验用状态机来控制-The experiment is driven FPGA adc0804 this chip, the chip to be used as drivers have a certain timing control, so the state machine to control the experiment
example9
- 用 epm240 驱动 adc0804 这个芯片,本实验用状态机来控制。-Epm240 Driver adc0804 with this chip, the state machine to control the experiment.
URAT-hdlVHDL
- URTA 各种功能的时序仿真 包括配置 发射接收数据-URTA timing simulation of various functions, including transmitting and receiving data configuration
URAT_VHDL_CODE
- altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
DCT
- Discrete Cosine transform VHDL code, with a positive transformation within the inverse transform of the test file.
URAT_VHDL
- URAT VHDL程序与仿真，包括顶层程序与仿真，波特率发生器VHDL程序， UART发送器程序与仿真，UART接收器程序与仿真-URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simu
project2
- 能算出CRC32 Data width 32 bit 的HDL-Is able to calculate the CRC32 Data width 32 bit of the HDL