资源列表
sdram_controller_latest.tar
- sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is me
msp430_FPGAcommunicatecode
- 本代码是通过msp430f149与fpga实现的两者通信程序，包含自己设定的协议-This code is msp430f149 fpga implementation of both communication and procedures, contains its own set of protocols ..
LIP1721CORE_system_fuse
- System fuse verilog code
Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
vhdl_fft
- 一个用vhdl语言（硬件描述语言）编写的fft实现程序。fft用途很广，该程序可以在cpld或fpga等硬件上实现，软件坏境为maxplus10.0及以上或quartus2。
115157690vhdl_fft
- 基于FPGA的FFT转换，代码很全 可以进行综合-FPGA-based FFT conversion, the code is full to undertake a comprehensive
VHDL_commponet
- fpga设计中利用vhdl语言的元件例化语句和程序包可以优化代码，附有加法器，触发器的程序实例-plus and the other devices
Sequence-detector-design
- 序列检测器设计的思路大多都是用FSM来实现的,此思路是通过移位寄存器来实现序列检测-Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
Ultraedit_verilog
- 这个文件中提供了 verilog hdl 的在ultra edit32中编程所需要的语法
AD0809
- ADC0809是8位AD转换器，片内有8路模拟开关，可控制8个模拟量中的1个进入转换器中，完成一次转换的时间约100us。-ADC0809 is 8-bit AD converter, In the chip, there are 8-channel analog switches that can control one of eight analog quantity into converter, the time of a conversion is about 100us.
ARM_Instruction_Set
- Arm Instruction set document
Chebyshev-filter
- 主要介绍切比雪夫滤波器参数的计算，其主要特点是误差值在规定频段上等波纹变化-Introduces Chebyshev filter parameter calculation, the main feature is the error value in the upper band ripple requirement changes