资源列表
ADC_Ctrl
- 用verilog编写FPGA与AKM394A之间的接口程序-Verilog between FPGA and Ak5394A interface code
1UART
- Descr iption : Behavioral model of UART transmitter -- -- Model reads semicode from text file and performs UART transmissions -- Supports: -- outputs: TxD - UART Transmit Data-Descr iption : Behavioral model of UART transmitter --
adder_n
- 带进位加法器，这是照着书做的，解压以后就能在软件上仿真，没有错-This is "adder_n".
JK_flip_flop
- verilog编程的JK触发器，可以用modelsim进行仿真，附有测试程序-JK flip-flop
traffic
- VHDL语言设计的交通灯，具有黄灯等待功能。-VHDL language design of traffic lights, waiting for a yellow light function.
example1
- 分频程序：实现一个将时钟信号clk十分频的功能-Frequency program: to achieve a frequency of the clock signal clk is the function of
PWM
- pwm 懂得的人都知道它的重要性（单片机等） 我就不多说了 -pwm know how people know its importance (SCM, etc.) I do not say
16_multi
- 16*16有符号乘法器的 编码方式：Booth编码， 拓扑结构：简单阵列 加法器：Ripple Carry Adder
OpenSPARC_DDR2_controller_RTL_
- 基于FPGA的DDR2控制程序，用verilog编写的。,FPGA-based DDR2 control procedures, prepared by using Verilog.
JK
- 使用jk触发器来实现CMI码的编译码，延时小，操作方便-Using jk flip-flop to achieve the CMI code encoding and decoding, the delay is small, easy to operate
ECC in VHDL implementation
- Very Helpful algorithm to implement Elliptic Curve Cryptography in Hardware definition language
chip1
- CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL