资源列表
DCT_IDCT
- 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。
DINAMICALLY_PROGRAMMABLE_CACHE
- dynamically programmable cache memory for image processing applications
SPI-And-I2C-Convert
- verilog语言实现SPI协议和IIC协议之间的转换。-verilog language to implement the SPI protocol and the protocol conversion between the IIC.
syn_rst
- 指定同步复位时， always的敏感表中仅有时钟沿信号，仅仅当时钟沿采到同步复位的有效电平时，才会在时钟沿到达时刻进行复位操作-Specifies synchronous reset, always sensitive to the table is just a clock edge signal only when the clock along to pick active level synchronous reset, the clock edge arrival time will
fpga_vga_model
- vga基于fpga的两个使用使用实例 程序代码-vga fpga based on two instances of code that use
a_vhdl_can_controller
- Can use VHDL This source file may be used and distributed without //// --// restriction provided that this copyright statement is not //// --// removed from the file and that any derivative work contains //// --// the original copyright notice
VerilogHDL_advanced_digital_design_code_Ch8
- VerilogHDL_advanced_digital_design_code_Ch8 VerilogHDL高级数字设计源码Ch8
mid-term1
- Movahedin MIDTERM EXAM by me )-Movahedin MIDTERM EXAM by me )
DDDCCT_IDCTi
- 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包含VHDL及及Verilog版本。可用途JPEG及MEPG压缩算法 已通过测试。 -The discrete cosine transform and inverse discrete cosine transform HDL code and test files. Contains VHDL and Verilog versions. Can use JPEG and MEPG compression of algorithm has
fulladder
- 使用Vhdl语言实现数字电路全加器功能，算法比较简单，供初学者参考。-full adder
HighSpeedFIFOsInSpartan-IIFPGAs
- This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be chan
RF24L01yaokong
- MSP430F149—nRF24L01的全双工通信程序，发送端通过按键发送键值，接受端接受并用LCD显示。-MSP430F149-nRF24L01 full-duplex communication process, sender to send keys through the key, the receiving end to accept and use the LCD display.