资源列表
20060412183015974
- 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
SDHAnalysis
- 光纤通信中的SDH数据帧解析及提取的VHDL实现源代码，共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of VHDL source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extra
fulleradder
- 本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器．适合初学Modelsim的同行-Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder. Suitable for a novice counterparts Modelsim
compare_8
- Verilog HDL机器语言中八位比较器的实现，两个八位输入，一个一位的输出。-Eight machine language Verilog HDL source code comparison, two eight-bit input and output a bit.
directdigital
- this word document describes digital frequency synthesizer using VHDL
EP21_USB_FT245
- CycloneII I EP3C10E144 FPGA USB 驱动例程-CycloneII I EP3C10E144 FPGA USB driver routines
example2
- moore状态机程序 一共有四个状况，空闲 idle 等待 ready 信号准备好后进入判决状态 decision 否则继续等待 ready信号；判决状态 decision 中将 oe、we 信号置低，同时根据read_write 判定下一个状态是读状态 read 还是写状态 write；如果 read_write 为‘1’读状态 read，否则写状态write；读状态将oe 置高，we 置低；写状态将 oe 置低，we 置高。-moore state machine processes a
xilinxIDE
- xilinx fpga 下的IDE控制器原代码,贡献一起学习-xilinx fpga controller under the IDE source code and contribute to study together
ds18b20lcd1602
- 数字传感器ds18b20和lcd1602的源程序和仿真，实现温度的显示。-Digital sensor ds18b20 and lcd1602 the source and simulation, to achieve the temperature display.
primeno
- how to detect a prime number using VHDL
module
- 基于VHDL语言，设计7段LED液晶显示屏，可以下载到相关的xilinx开发板上进行验证-Based on the VHDL language, design 7 LED LCD screen, can be downloaded to the relevant board to verify the development of xilinx
modeldiv5
- 无分频电路，实现电路的五分频verilog代码，通过modelsim的仿真-No divider circuit circuit fifth frequency verilog code through modelsim simulation