资源列表
CLA
- carry look ahead adder
等精度数字频率计
- 等精度数字频率计，大连理工大学创新学院，看看吧-And other precision digital frequency meter, Dalian University of Technology Innovation Institute, take a look at it
CSA-_code
- CSA(Carry Select Adder) Code in VHDL
ClckGen
- Clock generator, simple desin
SAYEH
- core of a cpu that the of it,is sayeh
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
canbus
- CAN总线的FPGA实现源代码,Verilog语言实现-CAN Bus FPGA source code
CIC_deci4.rar
- cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
vhdl3
- VHDL Language Reference courses part3
NANDFLASH
- 用VHDL开发的NANDFLASH的读写程序,给出 NANDFLASH的时序正确的读写-NANDFLASH developed using VHDL to read and write the procedures, timing NANDFLASH give the correct reading and writing
hp 4140b
- hp 4140b VHDL编程
VHDL
- 分别采用行为描述，数据流描述和结构描述 编写的VHDL代码 同时，含有各自的testbench-Behavioral descr iptions were used, the data flow schema descr iption and VHDL code written at the same time, with their testbench