资源列表
7_DynDigTub
- FPGA，VHDL语言动态显示一位数码管，使用所有FPGA芯片，课重新分配引脚-FPGA, VHDL language dynamically display a digital tube, all FPGA chip, the lesson reallocate pin! !
RXER_PICO
- The program is used to establish communication with the pc through serial port. It utilses the inbuilt micro controller called as picoblaze for the processing for implementation on spartan 3E
tmp
- NIOS的IP核设计，可以实现针对于RTL8019AS的10兆网络接口控制，可进一步实现FPGA嵌入式网络开发应用-NIOS IP core design, can be achieved for RTL8019AS 10 trillion network interface control, further development and application of FPGA embedded network
UART
- 用verilog编写的串口程序。含发送与接收代码 波特率可选-Verilog write with the serial program. Including sending and receiving code baud rate can be chosen
bdpsk
- 基于CPLD的bpsk的调制系统，可以作为简单的实现模型-CPLD modulation system based on BPSK, can be used as a simple implementation model
lcm0.rar
- 入门，verilog语言，实现字符型液晶1602的显示，及按键控制,verilog
Ex_registrador_somador
- Registrador somador em vhdl (SUM register vhdl)
IDEinterface
- IDE接口时序和最全的接口定义，通过它可以实现硬盘的扇区读写-IDE interface timing and the most comprehensive interface definition, it can be achieved by sector hard disk read and write
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
sin_generate
- verilog 实现 dds正弦 函数信号发生器 verilog 实现 dds正弦 函数信号发生器-verilog achieve dds sine function signal generator verilog verilog dds sine function signal generator the dds sine function signal generator
vhdl-VGA
- VGA(Video Graphics Array)是IBM在1987年随PS/2机一起推出的一种视频传输标准，具有分辨率高、显示速率快、颜色丰富等优点-VGA (Video Array) is a little in 1987 IBM PS/2 machine together with launched a Video transmission standards, with high resolution, display speed is fast, and the color is ri
61EDA_D888
- 基于Verilog HDL出租车计费系统的研制-Based on Verilog HDL Taxi Accounting System