资源列表
Intro-VHDL-2
- intro VHDL 2 , electronic enginering
IFFT
- 用verilog语言实现OFDM信道发射部分的IFFT变换-OFDM channel transmitter part IFFT transform verilog language
VHDL_MIAOBIAO_CODE
- 基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码-CYCLONE series based on the FPGA EP1C3T144C8 stopwatch VHDL code
vga_dis
- verilog语言实现VGA接口显示，可以在显示器上显示几种图片，可以直接在quartus2上运行-verilog language display, VGA interface can display several pictures on the monitor, you can run directly in quartus2
FPGATutor
- FPGA 编程教程及例程，包含了FPGA程序编写教程并给出了相关例程，适于初学者-The Program Tutorial of FPGA, a plenty of examples are included which is quite useful for beginning learner
OFDM-FPGA-design
- OFDM系统数字中频的FPGA设计 本文主要讨论了 OFDM 系统中使用数字中频的优点, 在发射机和接收机中的 实现方案-The OFDM system digital IF FPGA design This paper mainly discusses the advantages of OFDM system using digital IF transmitter and receiver Implementation
ddsfpga
- 基于fpga的dds,特别好用，自己调试过了-Fpga based on the dds, particularly useful for their own after a commissioning
T01_UART_CORE
- Verilog 实现的 UART串口读写控制核 参数化校验、时钟设置，完整工程（xilinx），包括文档、源码等。供学习参考，希望大家上传自己代码，共同提高，*小日本。-Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation
led
- FPGA和VHDL的全过程和源码，有助你对FPGA和VHDL的认识和学习！
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
VGA_C
- VGA Test Screen in VHDL language
acounter
- 利用VHDL语言设计的等精度数字频率计，有各个模块的详细设计语言，已调试成功。-The use of VHDL language design digital frequency meter, a detailed design language of each module has been successful debugging.