资源列表
TrablholastPSD
- digital 24h clock on ise
JTD SJ
- 运用16位单片机所学的，LCD模块，小灯模块，定时器模块，串口通信模块。设计一个交通灯。(Using 16 bit MCU, LCD module, small lamp module, timer module, serial communication module. Design a traffic light.)
ProjetTentavive2
- Code (uncomplete) for a project I have, where I have to implement different processes in a Spartan3E card,in order to measure distance using ultrasonic emitters/receptors.
lcd11
- verilog 编写的lcd显示程序，结合spartan 3 an开发板，解压即可使用。-verilog written lcd display program, combined with the spartan 3 an development board, decompression can be used.
dig_clk1
- implementation of digital clock1
adder-8segmengt-display
- FPGA/CPLD开发，基于VHDL语言的加法器实现，并用数码管显示-FPGA/CPLD development, based on VHDL adder implementation, and use digital tube display
2LCD1602A
- FPGA VHDL 2LCD1602A VHDL实现-FPGA VHDL 2LCD1602A
hssdrc.tar
- 高速SDRAM控制器，并提供仿真测试程序和较详细的文档。
FrequencyMeasureV1.0
- Verilog写的相检宽带测频的IP及文档。-Verilog of frequency measurement
thunderbird
- 控制左右两对灯一次点亮，用状态机实现，verolog语言编写-Control about two lit the lamp again with the state machine implementation, verolog language
lcd_verilog
- 利用verilogＨＤＬ语言实现ＬＣＤ的驱动编程-Use of language implementation verilogHDL drive LCD programming
The-use-of-under-the-EDK-chipscope
- EDK下chipscope的使用，可以实时监控设计中的信号变化-EDK under chipscope use of real-time monitoring can change the design of the signal