资源列表
DCT_IDCT
- verilog code for DCT and IDCT (JPEG)
counter
- Counter for VHDL. I have made a 3 bit COunter for my stopwatch project. -Counter for VHDL. I have made a 3 bit COunter for my stopwatch project.
RVD.tar
- Realtime Video Display - Displaying real time video captured from a camera is an essential function in a vari- ety of applications ranging from CCTV se- curity monitoring to webconference meet- ings. In this project, we propose to build a s
dct
- JPEG Compression and Ethernet Communication on an FPGA
cy62127vll_70bai_vhdl_10
- SRAM CY62127DV30LL. vhdl model
saomiao
- verilog源代码，实现四个数码管蛇形循环显示-verilog source code, snake-like loop realization of the four digital displays
VHDL_TipsTricks
- Pong game development and implementation in VHDL
indus
- this book is a tutorial for indus soft
EDAmusicplayer
- EDA乐曲播放器,在EDA开发工具Quartus II 6.0平台上，采用VHDL语言层次化和模块化的设计方法，通过音符编码的设计思想，预先定制乐曲，实现动态显示乐曲演奏电路的设计-EDA music player
EDA3
- 实验目的 1．学习一般有限状态机的设计； 2．实现串行序列的设计。 二、设计要求 1． 先设计0111010011011010序列信号发生器； 2． 再设计一个序列信号检测器，若系统检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。 -Purpose of the experiment 1. Learning the general design of finite state machine 2. Serial sequence de
FPGA-basedimplementationoftherootraisedcosine
- 基于FPGA实现根升余弦滤波器的研究（在MATLAB环境中）-FPGA-based implementation of the root raised cosine filter (in the MATLAB environment)
reset
- 这是个关于同步复位和异步复位问题的探讨，最后得出同步释放，异步复位的效果最好 文件中有编好的verilog文件工程，以及仿真结果和RTL分析图，分析的很详细-This is a synchronous reset and asynchronous reset on the issue of the conclusion that synchronous release, asynchronous reset of the best documents are programmed veril