资源列表
jiafa
- 实现AD采样进来的5路信号相加、比较，判决，输出控制码 实现数字自动增益控制-AD sample the incoming signal sum, comparison, judgment, and output control codes to implement digital AGC
FPGA
- FPGA串口通信 Verilog -FPGA UART uartFPGA UART
FPGA_GOOD
- FPGA面试题目集锦 FPGA面试题目集锦-FPGA interview questions highlights FPGA interview subject highlights
state-machine-diagram
- 第6章 状态机图及其应用 Chapter 6 of the state machine diagram and its application-Chapter 6, the state machine diagram and its application of Chapter 6 of the state machine diagram and its application
ad7991
- ad7991驱动程序 适合于ad79XX系列芯片驱动-ad7991 driver suitable for ad79XX series chip driver
div16_dff
- 该项目用D触发器设计了一个基于VHDL的16分频的分频器，其中包括仿真时序图。-Of the project design with D flip-flop frequency divider 16 points based on VHDL, including simulation timing diagram.
frediv3
- 该工程设计了一个3分频器。电路结构由D触发器和与非门组成，包括工程完整，时序仿真图。-The project has designed a 3-divider. The circuit structure consists of a D flip-flop and NAND gate, including complete engineering simulation, timing diagram.
m_SSRG
- 该工程设计了一个m序列扩频系统，电路的结构为SSRG结构，已通过仿真。-The engineering design of an m-sequence spread spectrum system, the circuit structure of the SSRG structure has been through the simulation.
m_MSRG
- 该工程设计了一个扩频系统，采用原理图设计法，电路结构是MSRG，已通过仿真，并给出仿真时序图。-The engineering design of a spread spectrum system, the use of schematic design method, the circuit structure is MSRG has passed through the simulation, and simulation timing diagram.
div16_tff
- 该工程设计了一个16分频的分频器，电路采用T触发器，已通过仿真。-The engineering design of a 16 frequency divider circuit using T flip-flop, through simulation.
divide_testbench
- 除法描述，写的非常详细，真的很好用，可以作为一个工程的子模块使用-Descr iption of the division, written very detailed, really good, can be used as an engineering sub-module
add8
- 8位加法器 verilog + test bench-8 bits add