资源列表
VHDL-Cookbook.the.best
- This a Cookbook on VHDL. This is very simple to understand and comprehend-This is a Cookbook on VHDL. This is very simple to understand and comprehend
music
- 实现EDA硬件音乐播放，分别编写模块，代码简单易懂，适合初学者-EDA hardware music players, namely the preparation of modules, easy-to-understand code, suitable for beginners
Channel_Equalizer
- 使用Verilog编写的信道均衡器，可以有效解决抗多径问题，ISE12.2下编译通过-Written in Verilog channel equalizer can be an effective solution to anti-multipath, ISE12.2 compiled by
IFFT11111
- 使用Verilog编写的IFFT，ISE12.2下编译通过，学习IFFT核的同学可以参考-Use of the IFFT in Verilog compiler, ISE12.2 under study IFFT core students can refer to
Phase1111_Tracking
- 使用Verilog编写的相位跟踪器，可以有效解决锁相环中的相位跟踪问题，ISE12.2下编译通过-Written in Verilog phase tracker can effectively resolve the PLL phase tracking, ISE12.2 compiled by
Timing1111_Symcronization
- 使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过-Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by
Viterbi11111
- 使用Verilog编写的vertbi译码模块，ISE12.2下编译通过，主用是调用ISE下的Vertibi核设计实现的。-Written using Verilog vertbi decoding module, ISE12.2 compiled by the main use is to call ISE the nuclear Vertibi designed to achieve.
FPGA_Equalizer
- 使用Verilog编写的信道均衡器，可以有效解决抗多径问题，ISE12.2下编译通过-Written in Verilog channel equalizer can be an effective solution to anti-multipath, ISE12.2 compiled by
Fivelift-VHDL
- 用VHDL语言以及状态机实现五层电梯控制器。-VHDL language and the state machine to achieve the five-story elevator controller.
135geshili
- 135个经典设计实例基于Verilog，经典实用-135 classic examples of design based on Verilog
clock
- 基于VHDL的时钟设计，功能齐全，适合初学者参考。-VHDL-based clock design, the complete reference for beginners.
Traffic-light--Control-VHDL
- 用VHDL语言描述的实现十字路*通信号灯控制的程序。-Crossroads traffic lights control procedures described in VHDL language.