资源列表
MIMA
- 本程序是一个密码锁程序。包括四位密码的读取、识别、设置等。-This program is a combination lock program. Including four password to read, identification, setting, etc.
my_uart
- 用fpga实现串口通信，波特率通过计算后可以方便的设置-Serial communication, the baud rate calculation can be easily set using fpga
51CTODATALAYERPRODUCE
- 华为对于数据链路协议的介绍，对于初学者或有意了解华为的人，有很大的帮助。-Huawei for the introduction of data link protocol, a great help for beginners or people interested in understanding the Huawei.
fpgadds
- fpga的控制dds的程序，平率控制字及控制寄存器的控制-fpga control dds procedures, flat rate control word and control of the control register
vga_dis
- verilog语言实现VGA接口显示，可以在显示器上显示几种图片，可以直接在quartus2上运行-verilog language display, VGA interface can display several pictures on the monitor, you can run directly in quartus2
verilog-beijingdaxue
- 资料北大 fpga verilog 课件 内部资料 -FPGA verilog
mini1608_V2
- 基于STC12c的电子钟，12mHz晶振，16*08点阵-STC12c-based electronic clock, 12mHz crystal, 16* 08 dot matrix
Frequency_counter
- 频率计，带复位，先产生一个持续时间为一秒的的闸门信号，后计数开始，显示在LED上-Frequency counter with reset gate signal to produce a duration for the second, after the counting began, and displayed on the LED
DE2_70_NET
- 完成FPGA的网络通信，使用DM9000网络芯片 IP核，非常全面-DE2_70_NET，DM9000，can be used for communication with internet
reaction-time_FPGA_Verilog
- 基于FPGA的反应时间测试机——verilog HDL-Based on the reaction time test machine in the FPGA- Verilog the HDL
Choosing-signal-generator
- 基于FPGA的模拟信号源设计（中英文翻译） CPLD 信号发生器 频率捷变 无线电-FPGA signal generator frequency-agile
LCD-ok
- Hi, please open my account