资源列表
New
- VHDL Learning book Very Good
EDA
- 这是EDA上课用的全套课件，是学习eda课程系统的学习资料！-This is a complete set of EDA courseware used in class is learning the system of learning materials eda course!
4-16.doc
- 4-16译码器，用VHDL编写的，可以直接下载到可编程逻辑器件中-4-16 decoder, written with VHDL, can be directly downloaded to the programmable logic device
EXP12_VGA_img
- vga显示图片 读ROM中的数据 通过vga显示在显示器上-vga_color
jiyuxianxfzmdymqyj
- 基于VHDL的线性分组码编译码器设计-jiyuVHDLdexianxinfzm
ImplementationofHighSpeedUpDownConversionFIRFilter
- 为了对FPGA 的资源占用量最小，以便实现 片上系统(SoC)设计，充分利用了上下变频过程中I，Q 数据流的特点，仅用一套滤波器运算单元分时复用对I，Q 滤波，同时详细研究了滤波器的转置结构和位平面结构对FPGA资源占用量的差别。-Benefiting from the characteristics of I and Q data streams in the converter。 one set of computation units is multiplexed to fil
CPU
- 基于32位MIPS流水线CPU，由自己独立完成，-Pipelined 32-bit MIPS-based CPU, by themselves independently,
fifo_syn
- 本源码是用VERILOG实现FIFO的读取，并在实验板上已经验证可以使用-This source is used to achieve FIFO read VERILOG, and the board has been verified in experiments using
source
- 本源码是 基于VERILOG的SDRAM的开发与实现 并能实现 刷新，预充电，突发长度为8字节等功能 已验证，可用-The source is based on the SDRAM VERILOG development and implementation and to achieve refresh, precharge, a burst length of 8 bytes and other functions have been verified, the available
FPGA_Drive_VGA
- 介绍了VGA图形的显示原理及时序参数，并给出了FPGA产生时序驱动VGA的Verilog例程，适合初学者研读！-Introduced the principle of VGA graphics display and timing parameters, and generate timing-driven FPGA gives the VGA' s Verilog routines read suitable for beginners!
A_VGA_display_controller
- 详细介绍了VGA图像的驱动原理、时序参数，也给出了实现时序的HDL代码-Detail driving principle of the VGA image, timing parameters, but also to achieve given the timing of the HDL code
uCore_120rel_vhdl_f
- uCore architecture (VHDL and Forth sources). MicroCore s top priority is simplicity and understandability. MicroCore is rooted in the Forth language but it is not confined to execute Forth programs – it is a pretty good general purpose processor an