资源列表
music
- 自己做的音乐播放器 VHDL的 慢慢听 梁山伯与祝英台-Make their own music player to listen to VHDL' s slowly Butterfly Lovers
udcounter.v
- this program is for 8 bit up counter
nios_dds
- 采用Altera的NIOS内核，配合独立的累加器，实现了正弦波，三角波，锯齿波和方波的DDS产生电路，系统时钟最高可达120MHz，配合高速DAC，可产生最高约40MHz左右的波形-Using Altera' s NIOS core, with a separate accumulator, to achieve a sine wave, triangle wave, sawtooth and square wave generation circuit DDS system clock
AlteraFPGA_CPLD1
- Altera FPGA_CPLD设计 基础篇[1]\AlteraFPGA_CPLD1-Altera FPGA_CPLD Design Basics [1] \ AlteraFPGA_CPLD1
SATA
- sata标准很好的资料,以及介绍其当前的应用还有使用的注意事项-excellent information and descripiton of SATA protocol
SDRAM
- 对SDRAM通信协议进行了介绍，而且比较详细，还包含了ALTERA的部分芯片-some information and descr iption about SDRAM
Logicsynthesis
- 台湾的介绍逻辑综合的相当有价值的ppt资料-describe the steps of logic synthesis
VERILOG_VLSI_LAB_MANUAL
- VHDL Lab Manual useful for lab purpose
lab
- VHDL Lab manual useful for experiment purpose
cdngo
- MP3 Code Converter program
Design-of-general-purpose-registers-vhdl-language.
- 寄存器设计，以VHDL语言设计模拟一个通用寄存器。可供初学者学习。-Register is designed to simulate a VHDL language design general-purpose registers. For beginners to learn.
messageschedule
- Para calcular las palabras de cada ronda del algoritmo SHA