资源列表
UART
- A sample that describe how to make wiring between modules using verilog ,it contain two stages of inverter of SW1 as input and LD7 as output
MSP430C
- 用FPGA实现JPEG的Verilog源代码-JPEG with the FPGA implementation of the Verilog source code
exp_cpu_vhd
- cpu模型，除了时序和显示模块，有两个warning-A CPU module except downloading parts,such as SHIXU and XIANSHI.This version has 2 warning as below.But functional waveform shows --a right execution of computing. --ZHANG Hongjie 2010.6.11 -- Warning: Inf
verilog_16_SRAM
- 一个很好的Verilog测试sram程序-Verilog test sram
verliog_VGA
- verilog实现 VGA视频输出 ：直接输出到CRT，场频60，行频36-verilog to vga
verilog_DA_TLC5615
- verilog 写的硬件示波器设计检测频率为1K~10KHz-verilog 1K~10KHz test
EDACLOCK
- 一份关于EDA设计数字时钟的报告，与大家分享，希望对大家有帮助-EDA design of a digital clock on the report, to share, we want to help
jiaocheng
- 该文档描述了数字系统下的各种设计实验的原理及其源代码-This document describes a variety of digital system design principle of the experiment and its source code, etc.
FIR_matlab_verilog
- matlab 仿真低通滤波器，然后用verilog硬件实现-using matlab to simulate a fir lowpass, then using verilog to implement it.
shuzishizhongsheji
- 全新的数字时钟设计，适合学生们交作业，希望大家能喜欢-The new digital clock design, suitable for students who hand in papers, I hope you like
EDA_vhdl-SINE_COSINE_CODE
- 三角函数在FPGA中的实现，采用VHDL语言编写.-Trigonometric functions in the FPGA implementation, the use of VHDL language。
SDRAM
- FPGA SDRAM控制器Verilog源码，通过测试-FPGA SDRAM VERILOG