资源列表
du
- 通过IDE接口实现硬盘扇区的写操作，DMA方式的源代码-write operation to hard disk sector through the IDE interface , DMA mode of the source code
qiduanshumaguandongtaixianshi0000-9999
- 七段数码管动态显示 采用vhdl语言设计 编译 已通过-Seven-Segment LED dynamic display design using vhdl language compiler has passed
01chufaqi
- 带同步清0、同步置1 的D 触发器 verilog语言描述的-0 with synchronous clear, synchronous set 1 D flip-flop verilog language descr iption
miaobiao
- 秒表 数码管显示 采用verilog语言编写 Quartus II 9.0sp2 编译成功后生成的所有文件已包含-Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
src
- FIR滤波器的设计，完整包括RTL代码、testbench等，清晰易懂。-FIR filter design, complete coverage of RTL code, testbench, etc., clear and understandable.
fir_compiler
- FIR编译器。自动生成具有用户自定参数的FIR滤波器。 在 matlab里面设计滤波器，matlab里面设计输入字长。生成的rtl代码是该文件的头部有位宽宏定义，可以自行查阅。 -FIR Compiler. Automatically generate a user-defined parameters of FIR filters. Design a filter inside the matlab, matlab which design input word length. Rtl
debounce
- push button program that take 20ms afther that it load data
verilog_PLL
- verilog 写的硬件 pll 锁相环实现-verilog to pll
shumaguan
- 用按键控制选择6进制和9进制加法器，并用数码管显示。-Select 6 with keypad control, binary adder binary and 9, and with digital display.
FPGAarchitecturedesign8bi_CISCCPU
- FPGA架构的8位CISCCPU设计FPGA architecture design 8-bit CISCCPU-FPGA architecture design 8-bit CISCCPU
matlab-jiaocheng
- matlab教程，Matlab5.0手册上下-matlab tutorial, Matlab5.0 manual up and down