资源列表
cpudesignandreport
- 简单CPU VHDL实现 包含全部源码和报告-Simple CPU VHDL implementation and report that contains all the source code
Hspicesimple
- 不好意思 该站无HSPICE类型 书籍 所以无法选择分类 HSPICE简明教程-Sorry no HSPICE types of books to the station so I can not select the category HSPICE simple tutorial
OReillyHeadFirstObject-OrientedDesignandAnalysis.r
- OReilly Head First Object Oriented Design and Analysis pdf
uartverilog
- 该程序用VerilogHDL编写，主要用CPLD的EPM240T100C实现了RS-232的通信，供大家参考-VerilogHDL written by the program, mainly realized by CPLD' s EPM240T100C RS-232 communications for your reference
multiplier
- 采用移位相加方法设计的串行乘法器，具有握手信号（输入启动信号，输出完成信号），采用状态机方法设计的源代码。-A serial multiplier with a handshake signals (input start signal, the output completion signal), designed by adder and shifter using a state machine.
CPUInterfaceDesignWithVHDL
- 采用VHDL设计的CPU接口电路，源代码-CPU interface circuit, Designed using VHDL。 the source code
PING
- 一个甲、乙双方参赛，裁判参与的乒乓球比赛游戏模拟机。用8个发光二极管排成一条直线，以中点为界，两边各代表参赛双方的位置，其中点亮的发光二极管代表“乒乓球”的当前位置，点亮的发光二极管依次由左向右或由右向左移动。当球运动到某方的最后一位时，参赛者应立即按下自己一方的按钮，即表示击球，若击中，则“球”向相反方向运动，若未击中，则对方得1分。设置自动计分电路，双方各用二位数码管来显示计分，每局11分。每人发2球，7局4胜制。自动几分并显示-A A, B both play, the referee i
Goldenguid_Verilog
- Verilog黄金指导（中英文版本）,费了好大劲才找到，发扬共享精神~-Verilog Golden guidance (in English), take a great job finding and carry forward the spirit of sharing ~
Altera_FPGA_CPLD_Designing(Advanced)
- Altera FPGA_CPLD设计(高级篇) Altera FPGA/CPLD学习的优秀参考书-Altera_FPGA_CPLD_Designing(Advanced)
uart_rar_testbench
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.