资源列表
dzqfinal
- 基于vhdl的电子琴源程序， 基于vhdl的电子琴源程序。-Vhdl source code based on the organ, the organ-based vhdl source code, based on vhdl source of the organ.
shiyan7_12
- 设计一个数字时钟，具有按秒走时功能，能够分别显示小时（2位24小时）、分种（2位）、秒（2位）的功能，以及整点报警功能-Design a digital clock with seconds to go by when the function that displays hours, respectively (two 24-hour), minutes (2), second (2) function, and the whole point of the alarm function
vgachar
- VGA显示程序VHDL版本，适用于ALTERA的CPLD-VGA display program applies ALTERA CPLD
shumaguandongtaixianshi
- FPGA数码管实验veilog代码实现，经过验证成功运行-FPGA digital control experiment veilog code, a proven successful operation
interleaver
- 基于quartus软件的交织编码的仿真，应用于基带发射机的交织-simulation of interleaved coded based on quartus software.application of interleaving to baseband transmitter
TLV-5626
- DA转换芯片TLV5626的驱动程序，调试通过-DA zhuanhuanxinpian TLV5626 dequdongchengxu ,tiaoshitongguo
FPGA_USB2.0设计
- 把FX2配置成从FIFO的模式， 配置为单片机工作时钟24M，端点2输出，字节1024，端点6输入，字节1024，信号全设置为低电平有效等。我们的模块驱动时钟我们配置成内部输出时钟，也就是让FX2给我们的设计当做时钟源，输出一个最大的配置时钟48M的时钟。(The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input
Seq_det_gray
- Seq_detector in gray encoding. FSM modelling
pcit32_verilog_lattice
- 这个我也太清楚是什么 反正师兄们说有用 发大家
FPGAshiyan(5)
- FPGA入门系列实验教程——实验五.LED花样彩灯-Getting Started with FPGA tutorial series of experiments- experiment five. LED Mood lights
07_piano
- altera FPGA 教程 电子琴 verilog 语言 实现-a piano basied on FPGA ! It is a good thing!
VGA
- 各种VGA的时序驱动！ -All kinds of VGA timing-driven! All kinds of VGA timing-driven!