资源列表
bit4_8
- 用verilog语言编写的串口通信程序， 可以和下位机其他串口通信，控制8位继电器的开关-Using verilog language serial communication program, and slave other serial communications, control eight relay switches
digital-adder-source-code
- FPGA的Altera Quartus II 利用汇编语言实现加法器数码管的现实程序源代码-The Altera Quartus II FPGA using assembly language to achieve the reality of digital adder source code
pci32target_sourcecode
- pcitarget的源代码，测试通过，消耗fpga资源较少，稳定运行
LCD2864
- 基于FPGA设计的驱动12864让其显示-FPGA-based design-driven display it 12864
add
- FPGA VERILOG 加法器，数码管显示-FPGA VERILOG the Adder, digital tube display
FPGAshiyan(6)
- FPGA入门系列实验教程——实验六读取按键信号-Getting Started with FPGA tutorial series of experiments- experiments six key signal read
design
- 移动目标识别与跟踪 移动目标识别与跟踪-Moving target identification
sta1
- 有限状态机是根据当前状态以及触发条件进行状态转换的一种机制，包含一组状态集(state)、一个起始状态(start state)-Finite state machine is based on the current status and conditions trigger a state transition mechanism, contains a set of states (state), an initial state (start state)
jiao_tong
- FPGA和VHDL的全过程和源码，有助你对FPGA和VHDL的认识和学习！
signal_generator
- 信号发生器 可以通过该程序产生对应的波形 用Verilog语言编写实现 希望能对大家有帮助-The signal generator can generate through the program corresponding to the waveform using the Verilog language
EDA_PCI
- 硬件描述语言实现PCI控制器的ipcore设计-ues Hardware descr iption language to design PCI control
Multiple_ATD
- 基于Mc9s12xs128的多通道AD转换，这是驱动程序，使用时要配合LCD显示转换出来的电压值！-Mc9s12xs128 based multi-channel AD converter, which is the driver, when used with the LCD display to convert out of the voltage!