资源列表
ch9sch.ZIP
- Schematic of circuit in wakerly book
ch6sch
- Another Schematic Circuit
ch4sch
- another schematic circuit from wakerly
Buffer8x32
- Para controlar el flujo del algoritmo SHA
CH_Function
- Para calcular la funcion CH del algoritmo SHA
MAJ_Function
- Para calcular la funcion MAJ del algoritmo SHA
unidadcontrol
- Para la unidad de control del algoritmo SHA
msl16_vhdl
- It is CPU procesor in vhdl code. made in lithuania by students of europa
filter
- 基于HDL的3*3图像窗口滤波器,实现并行处理，达到图像平滑效果-3*3filter
huawei
- 华为大规模集成电路设计原则 很重要的一些设计人需要注意的原则-Huawei' s principles of large scale integrated circuit design is important
Testbench(Verilog)
- verilog验证平台的使用 很不错 很详细 想具体-verilog verification platform is more like using a very good specific
dividerverilogdesign
- verilog 分频器设计 偶数分频器和奇数分频器-divider verilog design even and odd divider divider