资源列表
SONGYFQ
- 用VHDL设计的电路，输出接到喇叭可播放乐曲“一分钱”。适合做课程设计。-Circuit design with VHDL, output to speakers can play music, " a penny." Suitable curriculum design.
soft_demapper
- This is soft demapper algorithm
jiaotongdeng
- 使用quartus2实现的交通灯控制，包括各个模块实现及总体实现-traffic light
verilog_uart_log_vhdl_uart_log
- verilog uart mode code VHDL uart mode -verilog uart mode code VHDL uart mode code VHDL uart mode
verilog_uart_log_vhdl_uart_logfdj
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
uart_rar_testbenchfidsof
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
example_VHDL
- VHDL 语言的初级实例，27个。电子钟，mask，ask-VHDL, the primary instance, 27. Electronic clock, mask, ask ... ...
an500
- Altera官方网站提供的NANFLASH接口的设计文档，很实用。-Altera official website of the NANFLASH interface design documents, it is practical.
pc
- 程序计数器+地址寄存器，已预置一段mif文件，可实现加法运算。-Program Counter+ address register, a mif file has been preset, addition operations can be realized.
processor
- 文件中包含一个简单MIIPS CPU的Verilog源代码-File contains a simple MIIPS CPU in Verilog source code
dff
- 用VHDL语言编写的带进位、置位、复位的D触发器，异步清零D触发器，同步清零D触发器-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity exp7_10 is port( clk: in std_logic d: in std_logic clr: in std_logic en,s:in std_logic q: o
d_ff
- 带置位、清零使能的D触发器以及同步清零D触发器、异步清零D触发器-VHDL，DFF