资源列表
signal_generator
- 基于FPGA的信号发生器的verilog实现-FPGA-based signal generator verilog implementation
clock
- 多功能数字钟：正常显示时分秒，设置调整时间，秒表，闹钟-Multifunctional digital clock: normal display, minutes and seconds, set to adjust the time, stopwatch, alarm clock
slave-0.4_VHDL
- i2c slave总线端*换 的设计与实现-i2c slave design
JK
- 带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器-With reset terminal, set end delay the 15ns CP' s response to the falling edge of the JK flip-flop
OFDM-16QAM
- 基于OFDM中的基带处理的16QAM调制，基于ISE编程软件,有完整的仿真程序-16QAM constellation mapping of the OFDM communication system
uart
- Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明，已接受到一个字节 output [7:0] rx_
decoding-circuit-of-the-digital-keys
- 数字按键译码电路VHDL语言描述，按下第一个键表示输入0，按下第二个键表示输入1，以此类推-VHDL language descr iption of the decoding circuit of the digital keys, press the first key input 0, press the second key input 1, and so on
vga
- 用VHDL写的vga串口实验，已经调试通过。-Vga serial experiments have been written using VHDL debugging through.
RGLight
- 本程序是基于VHDL的模拟交通灯程序，程序开发环境为ISE-This program is based on the the VHDL simulation traffic lights program, the program development environment for ISE
mxc_i2c
- 我自己学习i2c时在网上看的资料加理解后写的。-study i2c
6counter
- 六进制计数器，输入必需是二进制数.用555定时器来产生1HZ的信号脉冲，作为CP的输入信号-Hex counter, enter the required binary number. 1HZ signal pulse 555 timer to generate the input signal as the CP
nios-II
- NiosII范例，包括了DMA控制，串口通信，定时器中断，以及NIOS的部分范例，对于FPGA内核的开发很有帮助。-NiosII example, including the DMA control, serial communication, timer interrupt, as well as some examples of NIOS, development will be helpful for the FPGA core.